
LPC3250 Developer’s Kit - User’s Guide
Copyright 2010 © Embedded Artists AB
Connected to standard 20 pos (2x10 pin)
JTAG connector
Connected to standard 20 pos (2x10 pin)
JTAG connector
Positive reference for trimming potentiometer
Can be connected VDDA(V3A)
Negative reference for trimming potentiometer
LCDPWR signal, power enable for QVGA
display. Also connects to ETM pads, if
connector mounted.
LCDLE signal. Not used by design. Also
connects to ETM pads, if connector mounted.
LCDDCLK signal, dot clock for QVGA display.
Also connects to ETM pads, if connector
mounted.
LCDFP signal, vsync for QVGA display. Also
connects to ETM pads, if connector mounted.
LCDENAB signal, data enable for QVGA
display. Also connects to ETM pads, if
connector mounted.
LCDLP signal, hsync for QVGA display. Also
connects to ETM pads, if connector mounted.
LCD databit 4. Also connects to ETM pads, if
connector mounted.
LCD databit 5. Also connects to ETM pads, if
connector mounted.
LCD databit 6. Also connects to ETM pads, if
connector mounted.
LCD databit 7. Also connects to ETM pads, if
connector mounted.
Connected to push-button (for enabling
bootloader during reset or EINT0 input). Also
connects to LED (active low).
Connects to USB-to-serial bridge (for
automatic ISP functionality)
Enable UART
booting by pulling
signal low at reset
LCDCLKIN, an external clock signal can be
feed to this pin.
Connects to USB device/OTG interface
USB Device/OTG
i/f not used
Connects to USB host interface
USB Host interface
is connected to the
LPC3250
Connects to USB device/OTG interface
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